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4-channel, 12-/10-/8-bit adc with i 2 c-compatible interface in 8-lead sot-23 ad7991/ad7995/ad7999 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2010 analog devices, inc. all rights reserved. features 12-/10-/8-bit adcs with fast conversion time: 1 s typical 4 analog input channels/3 analog input channels with reference input specified for v dd of 2.7 v to 5.5 v sequencer operation temperature range: ?40c to +125c i 2 c-compatible serial interface supports standard, fast, and high speed modes 2 versions allow 2 i 2 c addresses low power consumption shutdown mode: 1 a maximum 8-lead sot-23 package applications system monitoring battery-powered systems data acquisition medical instruments functional block diagram i/p mux scl sda gnd ad7991/ad7995/ad7999 12-/10-/8-bit sar adc control logic and i 2 c interface v in0 v dd 06461-001 v in1 v in2 v in3 /v ref t/h figure 1. general description the ad7991/ad7995/ad7999 are 12-/10-/8-bit, low power, successive approximation adcs with an i 2 c?-compatible interface. each part operates from a single 2.7 v to 5.5 v power supply and features a 1 s conversion time. the track-and-hold amplifier allows each part to handle input frequencies of up to 14 mhz, and a multiplexer allows taking samples from four channels. each ad7991/ad7995/ad7999 provides a 2-wire serial interface compatible with i 2 c interfaces. the ad7991 and ad7995 come in two versions and each version has an individual i 2 c address. this allows two of the same devices to be connected to the same i 2 c bus. both versions support standard, fast, and high speed i 2 c interface modes. the ad7999 comes in one version. the ad7991/ad7995/ad7999 normally remain in a shutdown state, powering up only for conversions. the conversion process is controlled by a command mode, during which each i 2 c read operation initiates a conversion and returns the result over the i 2 c bus. when four channels are used as analog inputs, the reference for the part is taken from v dd ; this allows the widest dynamic input range to the adc. therefore, the analog input range to the adc is 0 v to v dd . an external reference, applied through the v in3 /v ref input, can also be used with this part. product highlights 1. four single-ended analog input channels, or three single- ended analog input channels and one reference input channel. 2. i 2 c-compatible serial interface. standard, fast, and high speed modes. 3. automatic shutdown. 4. reference derived from the power supply or external reference. 5. 8-lead sot-23 package. table 1. related devices device resolution input channels ad7998 12 8 ad7997 10 8 ad7994 12 4 ad7993 10 4 ad7992 12 2
ad7991/ad7995/ad7999 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 ad7991 .......................................................................................... 3 ad7995 .......................................................................................... 5 ad7999 .......................................................................................... 7 i 2 c timing specifications............................................................ 9 absolute maximum ratings.......................................................... 11 esd caution................................................................................ 11 pin configuration and function descriptions........................... 12 typical performance characteristics ........................................... 13 terminology .................................................................................... 16 theory of operation ...................................................................... 17 converter operation.................................................................. 17 typical connection diagram ................................................... 18 analog input ............................................................................... 18 internal register structure ............................................................ 20 configuration register .............................................................. 20 sample delay and bit trial delay............................................. 21 conversion result register ....................................................... 21 serial interface ................................................................................ 22 serial bus address...................................................................... 22 writing to the ad7991/ad7995/ad7999.................................. 23 reading from the ad7991/ad7995/ad7999............................ 24 placing the ad7991/ad7995/ad7999 into high speed mode................................................................................. 25 mode of operation......................................................................... 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 10/10rev. a to rev. b changes to max offset error parameter in table 2 ..................... 3 changes to max offset error parameter (y version) in table 3 ...... 5 changes to max offset error parameter (y version) in table 4 ...... 7 changes to ordering guide...................................................................27 10/09rev. 0 to rev. a changes to table 3............................................................................ 5 changes to table 4............................................................................ 7 updated ordering guide............................................................... 27 12/07revision 0: initial version
ad7991/ad7995/ad7999 rev. b | page 3 of 28 specifications ad7991 1 the temperature range of the y version is ?40c to +125c. unless otherwise noted, v dd = 2.7 v to 5.5 v, v ref = 2.5 v, f scl = 3.4 mhz, and t a = t min to t max . table 2. y version parameter min typ max unit test conditions/comments dynamic performance 2 , 3 see the sample delay and bit trial delay section, f in = 10 khz sine wave for f scl from 1.7 mhz to 3.4 mhz f in = 1 khz sine wave for f scl up to 400 khz signal-to-noise and distortion (sinad) 4 69.5 70 db signal-to-noise ratio (snr) 4 70 71 db total harmonic distortion (thd) 4 ?75.5 db peak harmonic or spurious noise (sfdr) 4 ?77.5 db intermodulation distortion (imd) 4 fa = 11 khz, fb = 9 khz for f scl from 1.7 mhz to 3.4 mhz fa = 5.4 khz, fb = 4.6 khz for f scl up to 400 khz second-order terms ?92 db third-order terms ?88 db channel-to-channel isolation 4 ?90 db f in = 10 khz full-power bandwidth 4 14 mhz @ 3 db 1.5 mhz @ 0.1 db dc accuracy 2 , 5 resolution 12 bits integral nonlinearity 4 1 lsb 0.5 lsb differential nonlinearity 4 0.9 lsb guaranteed no missed codes to 12 bits 0.5 lsb offset error 4 1 7 lsb offset error matching 0.5 lsb offset temperature drift 4.43 ppm/c gain error 4 2 lsb gain error matching 0.7 lsb gain temperature drift 0.69 ppm/c analog input input voltage range 0 v ref v v ref = v in3 /v ref or v dd dc leakage current 1 a input capacitance 34 pf channel 0 to channel 2during acquisition phase 4 pf channel 0 to channel 2outside acquisition phase 35 pf channel 3during acquisition phase 5 pf channel 3outside acquisition phase reference input v ref input voltage range 1.2 v dd v dc leakage current 1 a v ref input capacitance 5 pf outside conversion phase 35 pf during conversion phase input impedance 69 k
ad7991/ad7995/ad7999 rev. b | page 4 of 28 y version parameter min typ max unit test conditions/comments logic inputs (sda, scl) input high voltage, v inh 0.7 (v dd ) v v dd = 2.7 v to 5.5 v 0.9 (v dd ) v v dd = 2.35 v to 2.7 v input low voltage, v inl 0.3 (v dd ) v v dd = 2.7 v to 5.5 v 0.1 (v dd ) v v dd = 2.35 v to 2.7 v input leakage current, i in 1 a v in = 0 v or v dd input capacitance, c in 6 10 pf input hysteresis, v hyst 0.1 (v dd ) v logic outputs (open drain) output low voltage, v ol 0.4 v i sink = 3 ma 0.6 v i sink = 6 ma floating-state leakage current 1 a floating-state output capacitance 6 10 pf output coding straight (natural) binary throughput rate 18 (1/f scl ) f scl 1.7 mhz; see the serial interface section 17.5 (1/f scl ) + 2 s f scl > 1.7 mhz; see the serial interface section power requirements 2 v ref = v dd ; for f scl = 3.4 mhz, clock stretching is implemented v dd 2.7 5.5 v i dd digital inputs = 0 v or v dd adc operating, interface active (fully operational) 0.09/0.25 ma v dd = 3.3 v/5.5 v, 400 khz f scl 0.25/0.8 ma v dd = 3.3 v/5.5 v, 3.4 mhz f scl power-down, interface active 7 0.07/0.16 ma v dd = 3.3 v/5.5 v, 400 khz f scl 0.26/0.85 ma v dd = 3.3 v/5.5 v, 3.4 mhz f scl power-down, interface inactive 7 1/1.6 a v dd = 3.3 v/5.5 v power dissipation adc operating, interface active (fully operational) 0.3/1.38 mw v dd = 3.3 v/5.5 v, 400 khz f scl 0.83/4.4 mw v dd = 3.3 v/5.5 v, 3.4 mhz f scl power-down, interface active 7 0.24/0.88 mw v dd = 3.3 v/5.5 v, 400 khz f scl 0.86/4.68 mw v dd = 3.3 v/5.5 v, 3.4 mhz f scl power-down, interface inactive 7 3.3/8.8 w v dd = 3.3 v/5.5 v 1 functional from v dd = 2.35 v. 2 sample delay and bit trial delay enabled, t 1 = t 2 = 0.5/f scl . 3 for f scl up to 400 khz, cloc k stretching is not implemented. above f scl = 400 khz, clock stretc hing is implemented. 4 see the terminology section. 5 for f scl 1.7 mhz, clock stretching is not implemented; for f scl > 1.7 mhz, clock stretching is implemented. 6 guaranteed by initial characterization. 7 see the reading from the ad7991/ad7995/ad7999 section.
ad7991/ad7995/ad7999 rev. b | page 5 of 28 ad7995 1 the temperature range for the y version is ?40c to +125c. unless otherwise noted, v dd = 2.7 v to 5.5 v, v ref = 2.5 v, f scl = 3.4 mhz, and t a = t min to t max . table 3. a version 2 y version parameter min typ max min typ max unit test conditions/comments dynamic performance 3 , 4 see the sample delay and bit trial delay section, f in = 10 khz sine wave for f scl from 1.7 mhz to 3.4 mhz f in = 1 khz sine wave for f scl up to 400 khz signal-to-noise and distortion (sinad) 5 61.5 61 db total harmonic distortion (thd) 5 ?85 ?75 db peak harmonic or spurious noise (sfdr) 5 ?85 ?76 db intermodulation distortion (imd) 5 fa = 11 khz, fb = 9 khz for f scl from 1.7 mhz to 3.4 mhz fa = 5.4 khz, fb = 4.6 khz for f scl up to 400 khz second-order terms ?90 ?90 db third-order terms ?86 ?86 db channel-to-channel isolation 5 ?90 ?90 db f in = 10 khz full-power bandwidth 5 14 14 mhz @ 3 db 1.5 1.5 mhz @ 0.1 db dc accuracy 3, 6 resolution 10 10 bits integral nonlinearity 5 0.4 0.4 lsb differential nonlinearity 5 0.4 0.4 lsb offset error 5 1 2.25 lsb guaranteed no missed codes to 10 bits offset error matching 0.04 0.2 lsb offset temperature drift 4.13 4.13 ppm/c gain error 5 0.15 0.5 lsb gain error matching 0.06 0.25 lsb gain temperature drift 0.50 0.50 ppm/c analog input input voltage range 0 v ref 0 v ref v v ref = v in3 /v ref or v dd dc leakage current 1 1 a input capacitance 34 34 pf channel 0 to channel 2during acquisition phase 4 4 pf channel 0 to channel 2outside acquisition phase 35 35 pf channel 3during acquisition phase 5 5 pf channel 3outside acquisition phase reference input v ref input voltage range 1.2 v dd 1.2 v dd v dc leakage current 1 1 a v ref input capacitance 5 5 pf outside conversion phase 35 35 pf during conversion phase input impedance 69 69 k
ad7991/ad7995/ad7999 rev. b | page 6 of 28 a version 2 y version parameter min typ max min typ max unit test conditions/comments logic inputs (sda, scl) input high voltage, v inh 0.7 (v dd ) 0.7 (v dd ) v v dd = 2.7 v to 5.5 v 0.9 (v dd ) v v dd = 2.35 v to 2.7 v input low voltage, v inl 0.3 (v dd ) 0.3 (v dd ) v v dd = 2.7 v to 5.5 v 0.1 (v dd ) v v dd = 2.35 v to 2.7 v input leakage current, i in 1 1 a v in = 0 v or v dd input capacitance, c in 7 10 10 pf input hysteresis, v hyst 0.1 (v dd ) 0.1 (v dd ) v logic outputs (open drain) output low voltage, v ol 0.4 0.4 v i sink = 3 ma 0.6 0.6 v i sink = 6 ma floating-state leakage current 1 1 a floating-state output capacitance 7 10 10 pf output coding straight (natural) bi nary straight (natural) binary throughput rate 18 (1/f scl ) 18 (1/f scl ) f scl 1.7 mhz; see the serial interface section 17.5 (1/f scl ) + 2 s 17.5 (1/f scl ) + 2 s f scl > 1.7 mhz; see the serial interface section power requirements 3 v ref = v dd ; for f scl = 3.4 mhz, clock stretching is implemented v dd 2.7 5.5 2.7 5.5 v i dd digital inputs = 0 v or v dd 0.09/0.25 ma v dd = 3.3 v/5.5 v, 400 khz f scl adc operating, interface active (fully operational) 0.25 0.25/0.8 ma v dd = 3.3 v/5.5 v, 3.4 mhz f scl 0.07/0.16 ma v dd = 3.3 v/5.5 v, 400 khz f scl power-down, interface active 8 0.26 0.26/0.85 ma v dd = 3.3 v/5.5 v, 3.4 mhz f scl power-down, interface inactive 8 1 1/1.6 a v dd = 3.3 v/5.5 v power dissipation 0.3/1.38 mw v dd = 3.3 v/5.5 v, 400 khz f scl adc operating, interface active (fully operational) 0.83 0.83/4.4 mw v dd = 3.3 v/5.5 v, 3.4 mhz f scl 0.24/0.88 mw v dd = 3.3 v/5.5 v, 400 khz f scl power-down, interface active 8 0.86 0.86/4.68 mw v dd = 3.3 v/5.5 v, 3.4 mhz f scl power-down, interface inactive 8 3.3 3.3/8.8 w v dd = 3.3 v/5.5 v 1 functional from v dd = 2.35 v. 2 a version tested at v dd = 3.3 v and f scl = 3.4 mhz. functionality tested at f scl = 400 khz. 3 sample delay and bit trial delay enabled, t 1 = t 2 = 0.5/f scl . 4 for f scl up to 400 khz, cloc k stretching is not implemented. above f scl = 400 khz, clock stretc hing is implemented. 5 see the terminology section. 6 for f scl 1.7 mhz, clock stretching is not implemented; for f scl > 1.7 mhz, clock stretching is implemented. 7 guaranteed by initial characterization. 8 see the reading from the ad7991/ad7995/ad7999 section.
ad7991/ad7995/ad7999 rev. b | page 7 of 28 ad7999 1 the temperature range for the y version is ?40c to +125c. unless otherwise noted, v dd = 2.7 v to 5.5 v, v ref = 2.5 v, f scl = 3.4 mhz, and t a = t min to t max . table 4. a version 2 y version parameter min typ max min typ max unit test conditions/comments dynamic performance 3 , 4 see the sample delay and bit trial delay section, f in = 10 khz sine wave for f scl from 1.7 mhz to 3.4 mhz f in = 1 khz sine wave for f scl up to 400 khz signal-to-noise and distortion (sinad) 5 49.5 49.5 db total harmonic distortion (thd) 5 ?65 ?65 db peak harmonic or spurious noise (sfdr) 5 ?65 ?65 db intermodulation distortion (imd) 5 fa = 11 khz, fb = 9 khz for f scl from 1.7 mhz to 3.4 mhz fa = 5.4 khz, fb = 4.6 khz for f scl up to 400 khz second-order terms ?83 ?83 db third-order terms ?75 ?75 db channel-to-channel isolation 5 ?90 ?90 db f in = 10 khz full-power bandwidth 5 14 14 mhz @ 3 db 1.5 1.5 mhz @ 0.1 db dc accuracy 3, 6 resolution 8 8 bits integral nonlinearity 5 0.04 0.1 lsb differential nonlinearity 5 0.05 0.1 lsb guaranteed no missed codes to eight bits offset error 5 0.3 0.5 lsb offset error matching 0.02 0.05 lsb offset temperature drift 4.26 4.26 ppm/c gain error 5 0.06 0.175 lsb gain error matching 0.03 0.06 lsb gain temperature drift 0.59 0.59 ppm/c analog input input voltage range 0 v ref 0 v ref v v ref = v in3 /v ref or v dd dc leakage current 1 1 a input capacitance 34 34 pf channel 0 to channel 2during acquisition phase 4 4 pf channel 0 to channel 2outside acquisition phase 35 35 pf channel 3during acquisition phase 5 5 pf channel 3outside acquisition phase reference input v ref input voltage range 1.2 v dd 1.2 v dd v dc leakage current 1 1 a v ref input capacitance 5 5 pf outside conversion phase 35 35 pf during conversion phase input impedance 69 69 k
ad7991/ad7995/ad7999 rev. b | page 8 of 28 a version 2 y version parameter min typ max min typ max unit test conditions/comments logic inputs (sda, scl) input high voltage, v inh 0.7 (v dd ) 0.7 (v dd ) v v dd = 2.7 v to 5.5 v 0.9 (v dd ) v v dd = 2.35 v to 2.7 v input low voltage, v inl 0.3 (v dd ) 0.3 (v dd ) v v dd = 2.7 v to 5.5 v 0.1 (v dd ) v v dd = 2.35 v to 2.7 v input leakage current, i in 1 1 a v in = 0 v or v dd input capacitance, c in 7 10 10 pf input hysteresis, v hyst 0.1 (v dd ) 0.1 (v dd ) v logic outputs (open drain) output low voltage, v ol 0.4 0.4 v i sink = 3 ma 0.6 0.6 v i sink = 6 ma floating-state leakage current 1 1 a floating-state output capacitance 7 10 10 pf output coding straight (natural) bi nary straight (natural) binary throughput rate 18(1/f scl ) 18(1/f scl ) f scl 1.7 mhz; see the serial interface section 17.5(1/f scl ) + 2 s 17.5(1/f scl ) + 2 s f scl > 1.7 mhz; see the serial interface section power requirements 3 v ref = v dd ; for f scl = 3.4 mhz, clock stretching is implemented v dd 2.7 5.5 2.7 5.5 v i dd digital inputs = 0 v or v dd 0.09/0.25 ma v dd = 3.3 v/5.5 v, 400 khz f scl adc operating, interface active (fully operational) 0.25 0.25/0.8 ma v dd = 3.3 v/5.5 v, 3.4 mhz f scl 0.07/0.16 ma v dd = 3.3 v/5.5 v, 400 khz f scl power-down, interface active 8 0.26 0.26/0.85 ma v dd = 3.3 v/5.5 v, 3.4 mhz f scl power-down , interface inactive 8 1 1/1.6 a v dd = 3.3 v/5.5 v power dissipation adc operating, interface active (fully operational) 0.83 0.3/1.38 0.83/4.4 mw mw v dd = 3.3 v/5.5 v, 400 khz f scl v dd = 3.3 v/5.5 v, 3.4 mhz f scl 0.24/0.88 mw v dd = 3.3 v/5.5 v, 400 khz f scl power-down, interface active 8 0.86 0.86/4.68 mw v dd = 3.3 v/5.5 v, 3.4 mhz f scl power-down , interface inactive 8 3.3 3.3/8.8 w v dd = 3.3 v/5.5 v 1 functional from v dd = 2.35 v. 2 a version tested at v dd =3.3 v and f scl = 3.4 mhz. functionality tested at f scl = 400 khz. 3 sample delay and bit trial delay enabled, t 1 = t 2 = 0.5/f scl . 4 for f scl up to 400 khz, cloc k stretching is not implemented. above f scl = 400 khz, clock stretc hing is implemented. 5 see the terminology section. 6 for f scl 1.7 mhz, clock stretching is not implemented; for f scl > 1.7 mhz, clock stretching is implemented. 7 guaranteed by initial characterization. 8 see the reading from the ad7991/ad7995/ad7999 section.
ad7991/ad7995/ad7999 rev. b | page 9 of 28 i 2 c timing specifications guaranteed by initial characterization. all values were measured with the input filtering enabled. c b refers to the capacitive load on the bus line, with t r and t f measured between 0.3 v dd and 0.7 v dd (see figure 2 ) . unless otherwise noted, v dd = 2.7 v to 5.5 v and t a = t min to t max . table 5. limit at t min , t max parameter conditions min typ max unit description f scl 1 standard mode 100 khz serial clock frequency fast mode 400 khz high speed mode c b = 100 pf maximum 3.4 mhz c b = 400 pf maximum 1.7 mhz t 1 1 standard mode 4 s t high , scl high time fast mode 0.6 s high speed mode c b = 100 pf maximum 60 ns c b = 400 pf maximum 120 ns t 2 1 standard mode 4.7 s t low , scl low time fast mode 1.3 s high speed mode c b = 100 pf maximum 160 ns c b = 400 pf maximum 320 ns t 3 1 standard mode 250 ns t su;dat , data setup time fast mode 100 ns high speed mode 10 ns t 4 1 , 2 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s high speed mode c b = 100 pf maximum 0 70 3 ns c b = 400 pf maximum 0 150 ns t 5 1 standard mode 4.7 s t su;sta , setup time for a repeated start condition fast mode 0.6 s high speed mode 160 ns t 6 1 standard mode 4 s t hd;sta , hold time for a repeated start condition fast mode 0.6 s high speed mode 160 ns t 7 1 standard mode 4.7 s t buf , bus-free time between a stop and a start condition fast mode 1.3 s t 8 1 standard mode 4 s t su;sto , setup time for a stop condition fast mode 0.6 s high speed mode 160 ns t 9 standard mode 1000 ns t rda , rise time of the sda signal fast mode 20 + 0.1 c b 300 ns high speed mode c b = 100 pf maximum 10 80 ns c b = 400 pf maximum 20 160 ns
ad7991/ad7995/ad7999 rev. b | page 10 of 28 limit at t min , t max parameter conditions min typ max unit description t 10 standard mode 300 ns t fda , fall time of the sda signal fast mode 20 + 0.1 c b 300 ns high speed mode c b = 100 pf maximum 10 80 ns c b = 400 pf maximum 20 160 ns t 11 standard mode 1000 ns t rcl , rise time of the scl signal fast mode 20 + 0.1 c b 300 ns high speed mode c b = 100 pf maximum 10 40 ns c b = 400 pf maximum 20 80 ns t 11a standard mode 1000 ns t rcl1 , rise time of the scl signal after a repeated start condition and after an acknowledge bit fast mode 20 + 0.1 c b 300 ns high speed mode c b = 100 pf maximum 10 80 ns c b = 400 pf maximum 20 160 ns t 12 standard mode 300 ns t fcl , fall time of the scl signal fast mode 20 + 0.1 c b 300 ns high speed mode c b = 100 pf maximum 10 40 ns c b = 400 pf maximum 20 80 ns t sp 1 fast mode 0 50 ns pulse width of the suppressed spike high speed mode 0 10 ns t power-up 0.6 s power-up and acquisition time 1 functionality is tested during production. 2 a device must provide a data hold time for sda in order to bridge the undefined region of the scl falling edge. 3 for 3 v supplies, the maximum hold time with c b = 100 pf maximum is 100 ns maximum. t 6 t 7 t 2 t 11 t 4 t 1 t 12 t 10 t 5 t 9 t 6 t 3 t 8 0 6461-002 scl s sda s = start condition p = stop condition p p s figure 2. 2-wire serial interface timing diagram
ad7991/ad7995/ad7999 rev. b | page 11 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to gnd ?0.3 v to 7 v analog input voltage to gnd ?0.3 v to v dd + 0.3 v reference input voltage to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to +7 v digital output voltage to gnd ?0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature ranges industrial (y version) temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 8-lead sot-23 package ja thermal impedance 170c/w jc thermal impedance 90c/w rohs compliant temperature, soldering reflow 260 + 0c esd 1 kv 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7991/ad7995/ad7999 rev. b | page 12 of 28 pin configuration and fu nction descriptions 06461-003 scl 1 sda 2 v in0 3 v in1 4 v dd 8 gnd 7 v in3 /v ref 6 v in2 5 ad7991/ ad7995/ ad7999 top view (not to scale) figure 3. sot-23 pin configuration table 7. pin function descriptions pin no. mnemonic description 1 scl digital input. serial bus clock. external pull-up resistor required. 2 sda digital i/o. serial bus bidirectional data. op en-drain output. external pull-up resistor required. 3 v in0 analog input 1. single-ended analog in put channel. the input range is 0 v to v ref . 4 v in1 analog input 2. single-ended analog in put channel. the input range is 0 v to v ref . 5 v in2 analog input 3. single-ended analog in put channel. the input range is 0 v to v ref . 6 v in3 /v ref analog input 4. single-ended analog inp ut channel. the input range is 0 v to v ref . can also be used to input an external v ref signal. 7 gnd analog ground. ground reference point for all circui try on the ad7991/ad7995/ad7999. all analog input signals should be referred to this agnd voltage. 8 v dd power supply input. the v dd range for the ad7991/ad7995/ad7999 is from 2.7 v to 5.5 v. table 8. i 2 c address selection part number i 2 c address ad7991-0 010 1000 ad7991-1 010 1001 ad7995-0 010 1000 ad7995-1 010 1001 ad7999-1 010 1001
ad7991/ad7995/ad7999 rev. b | page 13 of 28 typical performance characteristics dnl error (lsb) code 0 500 1000 1500 2000 2500 3000 3500 4000 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 v dd = 2.7v v ref = 2.35v f scl = 1.7mhz 0 6461-005 figure 4. dnl error, v dd = 2.7 v, v ref = 2.35 v, f scl = 1.7 mhz without clock stretching inl error (lsb) code 0 500 1000 1500 2000 2500 3000 3500 4000 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 v dd = 2.7v v ref = 2.35v f scl = 1.7mhz 0 6461-006 figure 5. inl error, v dd = 2.7 v, v ref = 2.35 v, f scl = 1.7 mhz without clock stretching 12.0 8.0 06 reference voltage (v) enob (bits) sinad (db) 11.5 11.0 10.5 10.0 9.5 9.0 8.5 12345 60 62 64 66 68 70 72 74 enob v dd = 3v enob v dd = 5v sinad v dd = 5v sinad v dd = 3v 06461-036 figure 6. enob/sinad vs. reference voltage, f scl = 1.7 mhz without clock stretching 1.0 ?1.0 1.2 reference voltage (v) inl error (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 1.7 2.2 2.7 3.2 3.7 4.2 4.7 negative inl positive inl 06461-033 figure 7. inl error vs. reference voltage , f scl = 1.7 mhz without clock stretching 1.0 ?1.0 1.2 reference voltage (v) dnl error (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 1.7 2.2 2.7 3.2 3.7 4.2 4.7 negative dnl positive dnl 06461-037 figure 8. dnl error vs. reference voltage, f scl = 1.7 mhz without clock stretching inl error (lsb) code 0 500 1000 1500 2000 2500 3000 3500 4000 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 6461-013 v dd = 5v v ref = 2.5v f scl = 1.7mhz figure 9. inl error, v dd = 5 v, v ref = 2.5 v, f scl = 1.7 mhz without clock stretching
ad7991/ad7995/ad7999 rev. b | page 14 of 28 dnl error (lsb) code 0 500 1000 1500 2000 2500 3000 3500 4000 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 6461-014 v dd = 5v v ref = 2.5v f scl = 1.7mhz figure 10. dnl error, v dd = 5 v, v ref = 2.5 v, f scl = 1.7 mhz without clock stretching 800 0 26 v dd (v) i dd ( a) 345 f scl = 1.7mhz +125c +85c +25c ?40c 600 400 200 06461-035 figure 11. i dd supply current vs. supply voltage, f scl = 1.7 mhz without clock stretching, ?40c to +125c 1000 0 26 v dd (v) i dd ( a) 800 600 400 200 345 f scl = 3.4mhz +125c +85c +25c ?40c 06461-034 figure 12. i dd supply current vs. supply voltage, f scl = 3.4 mhz with clock stretching, ?40c to +125c ? 70 ?100 1 100 input frequency (khz) thd (db) ?80 ?90 f scl = 1.7mhz 06461-031 10 v dd = 5v v dd = 3v figure 13. thd vs. input frequency, v ref = 2.5 v, f scl = 1.7 mhz without clock stretching channel-to-channel isol a tion (db) f noise (khz) v dd = 3v v dd = 5v v ref = v dd f scl = 1.7mhz temperature = t a 89 90 91 92 93 94 95 96 0 102030405060708090100 0 6461-017 figure 14. ad7991 channel-to-channel isolation , f scl = 1.7 mhz without clock stretching ?120 ?100 ?80 ?60 ?40 ?20 0 0246810 sinad (db) frequency (khz) 06461-018 16384 point fft f s = 22.5ksps f scl = 405khz f in = 5.13khz snr = 71.83db sinad = 71.39db thd = ?81.26db sfdr = ?93.71db figure 15. dynamic performance, f scl = 405 khz without clock stretching, v dd = 5 v, full-scale input, seven-term blackman-harris window
ad7991/ad7995/ad7999 rev. b | page 15 of 28 06461-032 3 0 0 scl frequency (khz) power (mw) 500 1000 1500 2 1 v dd = 5v v dd = 3v ?120 ?100 ?80 ?60 ?40 ?20 0 0 5 10 15 20 25 30 35 40 45 sinad (db) frequency (khz) 0 6461-019 16384 point fft f s = 95ksps f scl = 1.71mhz f in = 10.13khz snr = 71.77db sinad = 71.45db thd = ?82.43db sfdr = ?95.02db figure 16. dynamic performance, f scl = 1.71 mhz without clock stretching, v dd = 5 v, full-scale input, seven-term blackman-harris window figure 17. power vs. scl frequency, v ref = 2.5 v
ad7991/ad7995/ad7999 rev. b | page 16 of 28 terminology signal-to-noise and distortion (sinad) ratio the measured ratio of signal-to-noise and distortion at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of the nonfundamental signals excluding dc, up to half the sampling frequency (f s /2). the ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. the theoretical sinad ratio for an ideal n-bit converter with a sine wave input is given by signal - to -( noise + distortion ) = (6.02 n + 1.76) db therefore, sinad is 49.92 db for an 8-bit converter, 61.96 db for a 10-bit converter, and 74 db for a 12-bit converter. total harmonic distortion (thd) the ratio of the rms sum of harmonics to the fundamental. for the ad7991/ad7995/ad7999, it is defined as 1 65432 v vvvvv thd 22222 log20)db( ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through sixth harmonics. peak harmonic or spurious noise the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. typically, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, the largest harmonic may be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n equals 0. for example, second-order terms include (fa + fb) and (fa ? fb), and third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7991/ad7995/ad7999 are tested using the ccif standard, where two input frequencies near the maximum input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of intermodulation distortion is, like the thd specification, the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in decibels. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between any two channels. it is measured by applying a full-scale sine wave signal to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 10 khz signal. the frequency of the signal in each of the unselected channels is increased from 2 khz up to 92 khz. figure 14 shows the worst-case across all four channels for the ad7991. full-power bandwidth the input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 db or 3 db for a full-scale input. integral nonlinearity the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints are at zero scale (a point 1 lsb below the first code transition) and full scale (a point 1 lsb above the last code transition). differential nonlinearity the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error the deviation of the first code transition (00 000 to 00 001) from the idealthat is, agnd + 1 lsb. offset error match the difference in offset error between any two channels. gain error the deviation of the last code transition (111 110 to 111 111) from the ideal (that is, v ref ? 1 lsb) after the offset error has been adjusted out. gain error match the difference in gain error between any two channels.
ad7991/ad7995/ad7999 rev. b | page 17 of 28 theory of operation the ad7991/ad7995/ad7999 are low power, 12-/10-/8-bit, single-supply, 4-channel adcs. each part can be operated from a single 2.35 v to 5.5 v supply. the ad7991/ad7995/ad7999 provide the user with a 4-channel multiplexer, an on-chip track-and-hold, an adc, and an i 2 c- compatible serial interface, all housed in an 8-lead sot-23 package that offers the user considerable space-saving advantages over alternative solutions. the ad7991/ad7995/ad7999 normally remains in a power- down state while not converting. therefore, when supplies are first applied, the part is in a power-down state. power-up is initiated prior to a conversion, and the device returns to the power-down state upon completion of the conversion. this automatic power- down feature allows the device to save power between conversions. this means any read or write operations across the i 2 c interface can occur while the device is in power-down. converter operation the ad7991/ad7995/ad7999 are successive approximation adcs built around a capacitive dac. figure 18 and figure 19 show simplified schematics of the adc during its acquisition and conversion phases, respectively. figure 18 shows the adc during its acquisition phase: sw2 is closed, sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on v in . the source driving the analog input needs to settle the analog input signal to within one lsb in 0.6 s, which is equivalent to the duration of the power-up and acquisition time. 06461-020 capacitive dac v in comparator control logic sw1 a b sw2 agnd figure 18. adc acquisition phase when the adc starts a conversion, as shown in figure 19 , sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced. the input is disconnected when the con- version begins. the control logic and the capacitive dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figure 20 shows the adc transfer function. 06461-021 v in comparator control logic sw1 a b sw2 agnd capacitive dac figure 19. adc conversion phase adc transfer function the output coding of the ad7991/ad7995/ad7999 is straight binary. the designed code transitions occur at successive integer lsb values (that is, 1 lsb, 2 lsb, and so on). the lsb size for the ad7991/ad7995/ad7999 is v ref /4096, v ref /1024, and v ref /256, respectively. figure 20 shows the ideal transfer characteristics for the ad7991/ad7995/ad7999. 111 ... 111 111 ... 110 111 ... 000 adc code agnd + 1 lsb analog input 0v to ref in ad7991 1 lsb = ref in /4096 ad7995 1 lsb = ref in /1024 ad7999 1 lsb = ref in /256 +ref in ? 1 lsb 011 ... 111 000 ... 010 000 ... 001 000 ... 000 06461-022 figure 20. ad7991/ad7995/ad7999 transfer characteristics
ad7991/ad7995/ad7999 rev. b | page 18 of 28 typical connection diagram figure 22 shows the typical connection diagram for the ad7991/ad7995/ad7999. the reference voltage can be taken from the supply voltage, v dd . however, the ad7991/ad7995/ad7999 can be configured to be a 3-channel device with the reference voltage applied to the v in3 /v ref pin. in this case, a 1 f decoupling capacitor on the v in3 /v ref pin is recommended. sda and scl form the 2-wire i 2 c compatible interface. external pull-up resistors are required for both the sda and scl lines. the ad7991-0/ad7995-0 and the ad7991-1/ad7995-1/ ad7999-1 support standard, fast, and high speed i 2 c interface modes. both the -0 and -1 devices have independent i 2 c addresses, which allows the devices to connect to the same i 2 c bus without contention issues. the part requires approximately 0.6 s to wake up from power- down and to acquire the analog input. once the acquisition phase ends, the conversion phase starts and takes approximately 1 s to complete. the ad7991/ad7995/ad7999 enters shutdown mode after each conversion, which is useful in applications where power consumption is a concern. analog input figure 21 shows an equivalent circuit of the ad7991/ad7995/ ad7999 analog input structure. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 300 mv. if the signal does exceed this level, the diodes become forward-biased and start conducting current into the substrate. each diode can conduct a maximum current of 10 ma without causing irreversible damage to the part. 06461-023 v in d1 v dd d2 r1 c2 30pf c1 4pf conversion phase?switch open track phase?switch closed figure 21. equivalent analog input circuit capacitor c1 in figure 21 is typically about 4 pf and can primarily be attributed to pin capacitance. resistor r1 is a lumped component composed of the on resistance (r on ) of both a track-and-hold switch and the input multiplexer. the total resistor is typically about 400 . capacitor c2, the adc sampling capacitor, has a typical capacitance of 30 pf. v in0 r p r p v dd 5v supply 10f 0.1f microcontroller/ microprocessor 2-wire serial interface gnd ad7991/ ad7995/ ad7999 sda scl 06461-024 v in1 v in2 v in3 /v ref + + figure 22. ad7991/ad7995/ad7999 typical connection diagram
ad7991/ad7995/ad7999 rev. b | page 19 of 28 for ac applications, removing high frequency components from the analog input signal is recommended by use of an rc band- pass filter on the relevant analog input pin. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op amp is a function of the particular application. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of thd that can be tolerated. thd increases as the source impedance increases and performance degrades. figure 23 shows the thd vs. the analog input signal frequency for different source impedances at a supply voltage of 5 v. 56? 5.1k ? 2k? 1.3k ? 240? 1 10 100 analog input frequency (khz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 thd (db) v dd = 5v v ref = v dd temperature = t a f scl = 1.7mhz 0 6461-025 figure 23. thd vs. analog input frequency for various source impedances for v dd = 5 v, f scl = 1.7 mhz without clock stretching
ad7991/ad7995/ad7999 rev. b | page 20 of 28 internal register structure configuration register the configuration register is an 8-bit write-only register that is used to set the operating modes of the ad7991/ad7995/ad7999. the bit functions are outlined in table 10 . a single-byte write is necessary when writing to the configuration register. d7 is the msb. when the master writes to the ad7991/ad7995/ad7999, the first byte is written to the configuration register. table 9. configuration register bit map and default settings at power-up d7 d6 d5 d4 d3 d2 d1 d0 ch3 ch2 ch1 ch0 ref_sel fltr bit trial delay sample delay 1 1 1 1 0 0 0 0 table 10. bit function descriptions bit mnemonic comment d7 to d4 ch3 to ch0 these four channel address bits select the analog input channel(s) to be converted. if a channel address bit (bit d7 to bit d4) is set to 1, a channel is selected for conversion. if more than one channel bit is set to 1, the ad7991/ad7995/ad7999 sequence through the selected channels, starting with the lowest channel. all unused channels should be set to 0. table 11 shows how these four channel address bits are decoded. prior to the device initiating a conversion, the channel(s) must be selected in the configuration register. d3 ref_sel this bit allows the user to select the supply voltage as the reference or choose to use an external reference. if this bit is 0, the supply is used as the reference, and the device acts as a 4-channel input part. if this bit is set to 1, an external reference must be used and applied to the v in3 /v ref pin, and the device acts as a 3-channel input part. d2 fltr the value written to this bit of the control register determines whether the filtering on sda and scl is enabled or bypassed. if this bit is set to 0, the filterin g is enabled; if it set to 1, the filtering is bypassed. d1 bit trial delay see the sample delay and bit trial delay section. d0 sample delay see the sample delay and bit trial delay section. table 11. channel selection d7 d6 d5 d4 analog input channel 1 0 0 0 0 no channel selected 0 0 0 1 convert on v in0 0 0 1 0 convert on v in1 0 0 1 1 sequence between v in0 and v in1 0 1 0 0 convert on v in2 0 1 0 1 sequence between v in0 and v in2 0 1 1 0 sequence between v in1 and v in2 0 1 1 1 sequence among v in0 , v in1 , and v in2 1 0 0 0 convert on v in3 1 0 0 1 sequence between v in0 and v in3 1 0 1 0 sequence between v in1 and v in3 1 0 1 1 sequence among v in0 , v in1 , and v in3 1 1 0 0 sequence between v in2 and v in3 1 1 0 1 sequence among v in0 , v in2 , and v in3 1 1 1 0 sequence among v in1 , v in2 , and v in3 1 1 1 1 sequence among v in0 , v in1 , v in2 , and v in3 1 the ad7991/ad7995/ad7999 converts on the select ed channel in the sequence in ascending order, starti ng with the lowest channel in the sequence.
ad7991/ad7995/ad7999 rev. b | page 21 of 28 sample delay and bit trial delay it is recommended that no i 2 c bus activity occur while a conversion is taking place (see figure 27 and the placing the ad7991/ad7995/ad7999 into high speed mode section). however, if this is not always possible, then in order to maintain the performance of the adc, bits d0 and d1 in the configuration register are used to delay critical sample intervals and bit trials from occurring while there is activity on the i 2 c bus. this results in a quiet period for each bit decision. however, the sample delay protection may introduce excessive jitter, degrading the snr for large signals above 300 hz. for guaranteed ac performance, use of clock stretching is recommended. when bit d0 and bit d1 are both 0, the bit trial and sample interval delay mechanism is implemented. the default setting of d0 and d1 is 0. to turn off both delay mechanisms, set d0 and d1 to 1. conversion result register the conversion result register is a 16-bit read-only register that stores the conversion result from the adc in straight binary format. a 2-byte read is necessary to read data from this register. table 1 2 shows the contents of the first byte to be read from ad7991/ad7995/ad7999, and table 13 shows the contents of the second byte to be read. each ad7991/ad7995/ad7999 conversion result consists of two leading 0s, two channel identifier bits, and the 12-/10-/8-bit data result. for the ad7995, the two lsbs (d1 and d0) of the second read contain two trailing 0s. for the ad7999, the four lsbs (d3, d2, d1, and d0) of the second read contain four trailing 0s. table 12. conversion value register (first read) d15 d14 d13 d12 d11 d10 d9 d8 leading 0 leading 0 ch id1 ch id0 msb b10 b9 b8 table 13. conversion value register (second read) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3/0 b2/0 b1/0 b0/0
ad7991/ad7995/ad7999 rev. b | page 22 of 28 serial interface control of the ad7991/ad7995/ad7999 is accomplished via the i 2 c-compatible serial bus. the ad7991/ad7995/ad7999 is connected to this bus as a slave device under the control of a master device, such as the processor. serial bus address like all i 2 c-compatible devices, the ad7991/ad7995/ad7999 has a 7-bit serial address. the devices are available in two versions, the ad7991-0/ad7995-0 and the ad7991-1/ad7995-1/ad7999-1. each version has a different address (see table 8 ), which allows up to two ad7991/ad7995 devices to be connected to a single serial bus. ad7999 has only one version. th e serial bus protocol operates as follows: 1. the master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line sda while the serial clock line, scl, remains high. this indicates that an address/data stream follows. 2. all slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit that determines the direction of the data transferthat is, whether data is written to or read from the slave device. 3. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is set to 0, the master writes to the slave device. if the r/ w bit is set to 1, the master reads from the slave device. 4. data is sent over the serial bus in sequences of nine clock pulseseight bits of data followed by an acknowledge bit from the receiver of data. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high may be interpreted as a stop signal. 5. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10 th clock pulse to assert a stop condition. in read mode, the master device pulls the data line high during the low period before the ninth clock pulse. this is known as a no acknowledge. the master takes the data line low during the low period before the 10 th clock pulse, and then high during the 10 th clock pulse to assert a stop condition. 6. any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix reads and writes in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.
ad7991/ad7995/ad7999 rev. b | page 23 of 28 writing to the ad7991/ad7995/ad7999 by default, each part operates in read-only mode and all four chan- nels are selected as enabled in the configuration register. to write to the ad7991/ad7995/ad7999 configuration register, the user must first address the device. the configuration register is an 8-bit register; therefore, only one byte of data can be written to this register. however, writing a single byte of data to this register consists of writing the serial bus write address, followed by the data byte written (see figure 24 ). scl sda start by master ack by adc r/w frame 1 serial bus address byte configuration register byte ack by adc stop 1 0 0 0 0 a0 d7 d6 d5 d4 d3 d2 d1 d0 11 99 1 06461-026 figure 24. writing to the ad7991/ad7995/ad7999 configuration register
ad7991/ad7995/ad7999 rev. b | page 24 of 28 reading from th e ad7991/ad7995/ad7999 reading data from the conversion result register is a 2-byte operation, as shown in figure 25 . therefore, a read operation always involves two bytes. after the ad7991/ad7995/ad7999 have received a read address, any number of reads can be performed from the conversion result register. following a start condition, the master writes the 7-bit address of the ad7991/ad7995/ad7999 and then sets r/ w to 1. the ad7991/ad7995/ad7999 acknowledge this by pulling the sda line low. they then output the conversion result over the i 2 c bus, preceded by four status bits. the status bits are two leading 0s followed by the channel identifier bits. for the ad7995 there are two trailing 0s, and for the ad7999 there are four trailing 0s. after the master has addressed the ad7991/ad7995/ad7999, the part begins to power up on the ninth sclk rising edge. at the same time, the acquisition phase begins. when approximately 0.6 s have elapsed, the acquisition phase ends. the input is sampled and a conversion begins. this is done in parallel to the read operation and should not affect the read operation. the master reads back two bytes of data. on the ninth sclk rising edge of the second byte, if the master sends an ack, it keeps reading conversion results and the ad7991/ad7995/ad7999 powers up and performs a second conversion. if the master sends a no ack, the ad7991/ad7995/ad7999 does not power up on the ninth sclk rising edge of the second byte. if a further conversion is required, the part converts on the next channel, as selected in the configuration register. see table 1 1 for information about the channel selection. if the master sends a no ack on the ninth sclk rising edge of the second byte, the conversion is finished and no further conversion is preformed. to put the part into full shutdown mode, the user should issue a stop condition to the ad7991/ad7995/ad7999. if the ad7991/ ad7995/ad7999 is not put into full shutdown mode, it will draw a few tens of microamperes from the supply. 06461-027 sda 11 9 9 d10 d9 d8 a0 1 000 00 0 scl 1 d11 1 d7 d6 d5 d2 d1 d0 d4 d3 scl (continued) sda (continued) ch id1 ch id0 r/w 9 start by master ack by adc no ack by master ack by master stop by master frame 1 serial bus address byte frame 2 most significant data byte from adc frame 3 least significant data byte from adc figure 25. reading two bytes of data from the ad7991conversion result register
ad7991/ad7995/ad7999 rev. b | page 25 of 28 placing the ad7991/ad7995/ad7999 into high speed mode high speed mode communication commences after the master addresses all devices connected to the bus with the master code, 00001xxx, to indicate that a high speed mode transfer is to begin. no device connected to the bus is allowed to acknowledge the high speed master code; therefore, the code is followed by a no ack (see figure 26 ). the master must then issue a repeated start, followed by the device address and an r/ w bit. the selected device then acknowledges its address. all devices continue to operate in high speed mode until the master issues a stop condition. when the stop condition is issued, the devices return to fast mode. to guarantee performance above f scl = 1.7 mhz, the user must perform clock stretchingthat is, the clock must be held highfor 2 s after the ninth clock rising edge (see figure 27 ). therefore, the clock must be held high for 2 s after the device starts to power up (see the reading from the ad7991/ad7995/ad7999 section). 0 6461-028 sda ack by adc start by master hs mode master code serial bus address byte no ack 19 1 9 01 0 0a0 xx100 0 scl 0 0 1 x sr fast mode high speed mode figure 26. placing the part into high speed mode 06461-030 s da 11 9 9 d10 d9 d8 a0 1 000 00 0 scl 1 d11 1 d7 d6 d5 d2 d1 d0 d4 d3 scl (continued) sda (continued) ch id1 ch id0 r/w 9 start by master ack by adc no ack by master ack by master stop by master frame 1 serial bus address byte frame 2 most significant data byte from adc frame 3 least significant data byte from adc clock high time = 2s figure 27. reading two bytes of data from the conversi on result register in high speed mode for ad7991
ad7991/ad7995/ad7999 rev. b | page 26 of 28 mode of operation the ad7991/ad7995/ad7999 powers up in shutdown mode. after the master addresses the ad7991/ad7995/ad7999 with the correct i 2 c address, the adc acknowledges the address. in response, the ad7991/ad7995/ad7999 power up. during this wake up time, the ad7991/ad7995/ad7999 exit shutdown mode and begin to acquire the analog input (acquisition phase). by default, all channels are selected. which channels are converted depends on the status of the channel bits in the configuration register. when the read address is acknowledged, the adc outputs two bytes of conversion data. the first byte contains four status bits and the four msbs of the conversion result. the status bits contain two leading 0s and two channel-identifier bits. after this first byte, the ad7991/ad7995/ad7999 outputs the second byte of the conversion result. for the ad7991, this second byte contains the lower eight bits of conversion data. for the ad7995, this second byte contains six bits of conversion data plus two trailing 0s. for the ad7999, this second byte contains four bits of conversion data and four trailing 0s. the master then sends a no ack to the ad7991/ad7995/ ad7999, as long as no further reads are required. if the master instead sends an ack to the ad7991/ad7995/ad7999, the adc powers up and completes another conversion. when more than one channel bit has been set in the configuration register, this conversion is performed on the second channel in the selected sequence. if only one channel is selected, the adc converts again on the selected channel. 06461-029 sr ra a second data byte (lsb) first data byte (msb) 7-bit address scl s da a 11 9 9 9 sr/p ack. by adc ack. by master no ack. by master figure 28. mode of operation, single-channel conversion
ad7991/ad7995/ad7999 rev. b | page 27 of 28 outline dimensions compliant to jedec standards mo-178-ba 121608-a 8 4 0 seating plane 1.95 bsc 0.65 bsc 0.60 bsc 76 1234 5 3.00 2.90 2.80 3.00 2.80 2.60 1.70 1.60 1.50 1.30 1.15 0.90 0 .15 max 0 .05 min 1.45 max 0.95 min 0.22 max 0.08 min 0.38 max 0.22 min 0.60 0.45 0.30 pin 1 indicator 8 figure 29. 8-lead small outline transistor package [sot-23] (rj-8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ad7991yrjz-1rl ?40c to +125c 8-lead sot-23 rj-8 c56 ad7991yrjz-1500rl7 ?40c to +125c 8-lead sot-23 rj-8 c56 ad7991yrjz-0rl ?40c to +125c 8-lead sot-23 rj-8 c55 ad7991yrjz-0500rl7 ?40c to +125c 8-lead sot-23 rj-8 c55 ad7995yrjz-1rl ?40c to +125c 8-lead sot-23 rj-8 c58 ad7995yrjz-1500rl7 ?40c to +125c 8-lead sot-23 rj-8 c58 ad7995yrjz-0rl ?40c to +125c 8-lead sot-23 rj-8 c57 ad7995yrjz-0500rl7 ?40c to +125c 8-lead sot-23 rj-8 c57 ad7995arjz-0rl ?40c to +125c 8-lead sot-23 rj-8 c6y ad7999yrjz-1rl ?40c to +125c 8-lead sot-23 rj-8 c5b AD7999YRJZ-1500RL7 ?40c to +125c 8-lead sot-23 rj-8 c5b ad7999arjz-1rl ?40c to +125c 8-lead sot-23 rj-8 c70 eval-ad7991ebz evaluation board eval-ad7995ebz evaluation board 1 z = rohs compliant part.
ad7991/ad7995/ad7999 rev. b | page 28 of 28 notes ?2007C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06461-0-10/10(b)

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